Optimizing the Performance of Full adder, NAND by the Use of Parameters of Nano Tube Carbon Field Effect Transistor Technology

Full adder and NAND are the most important parts of digital circuits. Therefore, optimizing the these blocks improves the whole output parameters of digital circuits. In this paper controversial full adder and NAND are designed in CNFET technology and then different parameters of CNFET technology are changed to optimize the speed and power consumption of full adder and NAND. The results of simulation by using HSPICE in .9v are presented. The result of simulation shows the best parameters for better performance of these full adder and NAND in CNFET technology.

Author(s): Seyedeh Somayeh Hatefinasab

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